1. Field of the Invention
The present invention relates to a data processor for executing a plurality of operations in parallel.
2. Description of Related Art
Recently, high performance processors utilizing a VLIW (Very Long instruction Word) technique and multimedia-oriented processors for processing digital signals effectively have been developed.
Although the VLIW technique enables parallel operations using hardware control simpler than the superscaler technique, it has a problem of increasing its code size generally. For example, when it executes an instruction that includes a plurality of operation codes and a field having no operation to be executed, it embeds into the field an operation code indicating no operation (NOP). Thus, the NOP code will increase the code size if no other steps are taken.
For example, U.S. Pat. No. 5,761,470 discloses a technique for reducing the code size by preparing a field for specifying a format (long format or short format) and an execution sequence of instructions. However, since the instructions must be executed sequentially according to the execution sequence specification, even if execution units are asymmetric and different execution units are used to perform the operations, the value of the operation code must have one-to-one correspondence with the content of the operation. If a field is prepared for specifying the execution units to execute the operations, it will be possible to assign different operations to the same operation code. In this case, however, the field for specifying the execution units will increase the code size.
Furthermore, reducing the number of instructions too much to shorten the basic instruction length presents another problem of making it difficult to achieve desired functions and performance. In addition, it presents another problem of increasing the code size oppositely because the number of instructions increases to achieve a given processing.
In summary, the conventional data processor with the foregoing configuration has the following problems: when the number of executable instructions is increased to enhance the performance, the code size increases; and when the number of instructions is reduced too much to shorten the basic instruction length, the desired functions and performance cannot be achieved.